Mittwoch, 29. Juni 2011


SoC (System on a Chip) is the name for a class of microelectronic designs which consist of several parts. Those parts were on different chips in former technologies, but now they are integrated on one silicon die. SoC is the heart of basically all modern electronic devices, like TV set, set-top box, smartphone, tablet and other. Integration of several chips into one is nothing new, older readers will remember how Intel integrated mathematical coprocessor into main processor and called this family of processors i486. But nowadays there are some new requirements for competitive designs which make designing a SoC a real challenge. The advantage of a SoC compared to several separate chips is higher communication speed between the parts, less space consumption, less energy consumption and hence less amount of heat to be dissipated. There is less wiring required on PCB and less elements means lower costs during manufacturing of the system.

A modern SoC consists of one or several micro processor cores, most likely ARM architecture, several interfaces, like DDR memory controller, USB 2.0, HDMI, I²C, CAN for car entertainment systems, hardware media decoder, 3D-graphic accelerator, analog-digital converter, even physical sensors for acceleration and alike. A single company can hardly develop all these parts alone, so it needs to buy IP from other companies. There are hard and soft IP macros: soft IP means just Verilog description of an IP (think of ARM core, which can be optimized timing wise) while hard IP means a complete layout for a specific technology (think of perfectly layouted USB controller). Since all parts are on the same die and are manufactured at once, all IPs must be available in the same technology of a certain foundry like TSMC. These many blocks introduce additional difficulty for developers of analog parts of the chip because analog parts are much more sensitive to variations during manufacturing. Moreover irregular analog structures cause more problems for lithography than regular digital structures in standard cells. There are solutions for this problem like SiP (System in a Package) or 3D-chips, where analog dies are ordered vertically or horizontally next to the digital die, but this means higher costs, since basically two chips must be manufactured and connected in a tight package. Another problem with integrating different functionalities mixing analog and digital parts is that these parts can disturb each other by injecting noise in substrate, by dissipating more heat on a smaller area as well as consuming more power in smaller areas. So if the power grid inside the design is not calculated carefully one part could soak more current and leave other parts underpowered.

But real challenges arise for SoC designer due to new requirements, which are necessary for a modern SoC design due to the fact that it has to be sold several million times in order to become profitable:

1. New interfaces - A SoC must be able to handle inputs from multi-touch displays, GPS satellites, Hall-sensors (magnetic compass), acceleration meters, light sensors, high resolution cameras, several wireless standards, and other input devices. It must drive high-resolution displays (eventually 3D), output hifi-quality audio, or give even physical feedback using actuators.

2. New possibilities for connectivity - A modern TV can connect to internet wirelessly as well as needs to connect to video input from several devices, like blue-ray player, set-top-box, game console. It has Firewire and USB interfaces for external hard-disks, several slots for memory cards. Connecting all these device types to a SoC must be handled by it.

3. New programmability – since the iPhone and its very successful AppStore concept everybody is talking about the app economy which means generation of revenue after sale of the product. Every smartphone series has its own AppStore, in foreseeable future TV and set-top producer will have their own, also AppStores from car manufacturer for their entertainment systems are expected. What does it mean for a SoC? A completely free programmable SoC must be tested more carefully because in advance it is not known which software will run on the system. Moreover since introduction of Windows for ARM several operation systems must be able to run on a SoC and support all its interfaces.

4. Low-Power - mobile systems need to run as long as possible on a single battery charge, also stationary devices should not consume too much power for environmental reasons. That means that parts of the device which are not needed at the moment can be switched off, must wake-up as soon as they are required and start communication with active parts.

Combining these requirements with advanced technology nodes, short time-to-market window, and the pressure to sell several millions of SoCs it becomes clear that some new approaches are needed rather than old ways like writing software and developing the hardware independently and bringing both together after the design has been produced. The amount of verification and testing of different configurations is basically exploding. In order to fulfill the requirements listed above the development of software and hardware must be tightly coupled. That means the software must be able to run on a model of the hardware design which resembles the functionality of the hardware as exact as possible. But here comes the necessary trade-off: it is possible to simulate the behavior of a single transistor and parasitic effects, but simulation of several millions transistors is simply not possible. So a higher abstraction level is necessary, which is still accurate enough to allow that the results are not too different from the produced silicon. Since a SoC consists of several IPs, one of the requirements of modern IPs is to have different models which can be used in simulation and verification of the whole system. If simulation is still too complex to be handled by software running on regular workstations, there are special hardware solutions, either based on FPGAs or special processor arrays, on this hardware the model of the system can be uploaded and emulated.

All big EDA companies started preparation in order to handle the new requirements. Synopsys bought two verification companies and is the biggest IP provider. Cadence started the EDA360 initiative in which it develops IPs with simulation models and creates partnerships with other IP companies like ARM. Mentor is becoming active in software business: it bought several Linux-oriented companies, so the promise here is to have tightly coupled soft- and hardware. Cadence and Mentor are also partnering in defining standards for verification of SoCs and both have powerful hardware based emulation solutions.

Due to the rising complexity and high manufacturing costs of a design in advanced technologies the main focus for chip industry is not development of the chip but integration of several parts into one design. Only a verified design with optimized drivers is competitive on todays market if it consumes less power and provides great multifunctionality.

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